1. Field of the Invention
This invention relates to a system for assigning block terminals, and more particularly to a system for optimizing block terminal positions when automatically designing a layout for a semiconductor device such as a VLSI.
2. Description of the Prior Art
In a semiconductor device such as a VLSI, generally, a plurality of blocks are disposed, and block terminals or pins are electrically connected via wirings. The assignment of the positions of such terminals is manually performed by a circuit designer while taking into account the connection of signals.
In the prior art, therefore, it is difficult to simultaneously satisfy the two requirements that the terminal positions are to be optimized to avoid the local concentration of the terminals and that the total wiring length is to be minimized. Furthermore, in a manual terminal location assignment process, such a problem is encountered that considerably increased manhours are required for designing the layout of a VLSI, creating the difficulty in reducing the designing period.